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INR

PhD in Computer Architecture and High-Performance Digital Circuit Design for Edge AI Computing

INRS University Edge Computing, Communication, and Learning (ECCoLe) Lab, INRS-EMT Research Centre
✓ Funded (Competition) ⏰ Closing Soon 🎓 Computer Engineering 🎓 Electrical Engineering edge computing computer architecture digital design machine learning optimization fpga asic development high-performance circuits hardware-aware machine learning

Explore novel designs in digital and computer architecture to boost edge AI computing. Develop hardware-aware machine learning techniques to optimize circuits for performance and efficiency in embedded systems.

AI-generated overview

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Why This Research Matters

This research addresses critical needs for energy-efficient and high-performance AI hardware at the edge, enabling real-time processing in telecommunications and embedded systems. It enhances the deployment of machine learning models on resource-constrained devices, promoting advances in autonomous systems and intelligent networks.

Computer Architecture High-Performance Architectures for Real-time Embedded Systems Hardware

Project Description

Project Overview

The PhD project focuses on the design and optimization of high-performance digital architectures and circuits tailored for edge computing applications in machine learning and telecommunications. Research includes developing efficient hardware-aware optimization techniques such as quantization and pruning to improve the performance and energy efficiency of deep learning systems.

What You Will Do

You will design digital circuits and systems using hardware description languages and FPGA/ASIC tools, optimize machine learning models for hardware implementation, and collaborate with interdisciplinary teams to develop novel edge computing solutions.

Expected Outcomes

The research aims to produce innovative high-efficiency circuit designs and optimization methods for real-time machine learning inference on embedded devices, potentially enhancing performance and reducing power consumption in practical applications.

Why This Matters

As AI moves toward decentralized and resource-constrained environments, this work supports the development of efficient edge devices. Improved architectures can enable faster and more reliable AI in telecommunications, autonomous systems, and embedded computing.

Entry Requirements

Master's degree in Computer Engineering or Electrical Engineering. Strong background in digital design and computer architectures. Proficiency in hardware description languages (VHDL, Verilog). Experience with FPGA and ASIC development tools. Programming knowledge in MATLAB, Python, or C++. Machine learning and optimization experience are assets. Good communication skills and ability to work independently and collaboratively.

How to Apply

Send a detailed CV and academic transcripts by email to shervin.vakili@inrs.ca with subject line "PhD Position – Computer Architecture INRS". Only shortlisted applicants will be contacted.

Eligibility

UK/Home
EU
International

Supervisor Profile

DS
Dr. Shervin Vakili
INRS University, Edge Computing, Communication, and Learning (ECCoLe) Lab, INRS-EMT Research Centre
300 Citations
14 h-index
Google Scholar

Dr. Shervin Vakili is an Assistant Professor at INRS-EMT specializing in computer architecture and high-performance architectures for real-time embedded systems. His research covers digital circuit design, hardware-aware machine learning, and energy-efficient architectures. He has multiple publications on optimization methods and accelerator designs in IEEE Transactions and top conferences.

Key Publications

2013 44 citations
Enhanced precision analysis for accuracy-aware bit-width optimization using affine arithmetic
2010 38 citations
Parallel scalable hardware implementation of asynchronous discrete particle swarm optimization
2018 26 citations
Power reduction in cnn pooling layers with a preliminary partial computation strategy
2021 25 citations
CARLA: A convolution accelerator with a reconfigurable and low-energy architecture
2016 13 citations
Memory-efficient string matching for intrusion detection systems using a high-precision pattern grouping algorithm

Research Contributions

Enhanced precision analysis techniques improve bit-width optimization using affine arithmetic, enabling more accuracy-aware hardware design.
This contributes to more efficient and precise computing hardware, which is important in embedded and real-time systems.
Developed parallel scalable hardware implementations of asynchronous discrete particle swarm optimization algorithms for improved computational optimization.
Enabled more efficient hardware solutions for complex optimization problems, benefiting real-time and high-performance applications.
Designed convolution accelerators with reconfigurable and low-energy architectures to reduce power consumption in CNN processing.
Supports development of energy-efficient AI hardware accelerators critical for embedded deep learning applications.
Proposed memory-efficient string matching algorithms suitable for intrusion detection systems that use high-precision pattern grouping.
Improves security-related monitoring techniques by optimizing hardware resource use and processing speed.

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